A 2.6-GHzE.2-GHz Frequency Synthesizer in 0.4-pm CMOS Technology

a 0.4-pm digit l CMOS technology entails many difficulties This paper describes the design of a CMOS frequency synthesizer targeting wireless local area network applications in the 5-GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-pm digital CMOS technology, the circuit provides a channel spacing of 23 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBdHz at 2.6 GHz and -100 dBdHz at 5.2 GHz at 10-MHz offset. The reference sidebands are at -50 dBc at 2.6 GHz and the power dissipation from a 2.6-V supply is 47 mW. at both the architecture and the circuit level. The high center frequency of the voltage-controlled oscillator (VCO), the poor quality of inductors due to skin effect and substrate loss, the limited tuning range, the nonlinearity of the VCO inputloutput characteristic, the high speed required of the dual-modulus divider, the mismatches in the charge pump, and the implementation of the loop filter are among the issues encountered in this design. In order to relax some of the synthesizer requirements, the transceiver and the synthesizer have been designed concurrently. Fig. 1 shows the transceiver architecture [2] and